Integrated circuit designers constantly strive to make the individual features within integrated circuits smaller so that the device density of the overall system can be improved. The ultimate size of devices in an integrated circuit is affected by the ability to create the photo mask used to implement the designed features, and by the ability to reproduce the masked features in the finished circuit. Typically, a standard cell library of macros for individual features is used to lay out the circuit. Various design rules are used to regulate the interactions among the macros. Problematically, standard cell library macros with high or low threshold voltage (Vt) transistors can be inefficient in their use of area. Also, the macros often have severe placement restrictions in an ASIC backplane. These inefficiencies are partly due to the design rules required to enable implant mask generation and subsequent use in a silicon fabrication process. The masks used for high Vt or low Vt implants have minimum width and space requirements. FIG. 1 (prior art) illustrates how these requirements may result in inefficient cell layout or placement. FIG. 1 shows a portion of an uncorrected layout indicated generally at 10. Features within the layout 10 that are not suitable for reproduction in a mask, such as the intersecting corners indicated at 12, create manufacturing difficulties. Design rules are used in order to avoid attempts to implement unmanufacturable layouts. A common approach taken in the arts in an effort to avoid this type of error is shown in FIG. 2 (prior art). The active area of the circuitry 14 used throughout the layout 11 is surrounded by an inactive area 16, avoiding the possibility of errors of a type (12) shown in FIG. 1. Although useful in preventing particular errors, this prior art approach leaves much to be desired in terms of efficient use of area.
Due to these and other problems, improved cell library macro layout methodology providing efficiencies in terms of design resources and area would be useful and advantageous in the arts. Accordingly, integrated circuit layout methods are provided that substantially eliminate or reduce some disadvantages associated with conventional methods.